Abstract
Tri-gate transistors offer better performance than planar transistors by exerting additional gate control over a channel from two lateral sides of semiconductor nanowalls (or ``fins''). Here we report the bottom-up assembly of aligned CdS nanowalls by a simultaneous combination of horizontal catalytic vapor-liquid-solid growth and vertical facet-selective noncatalytic vapor-solid growth and their parallel integration into tri-gate transistors and photodetectors at wafer scale (cm(2)) without postgrowth transfer or alignment steps. These tri-gate transistors act as enhancement-mode transistors with an on/off current ratio on the order of 10(8), 4 orders of magnitude higher than the best results ever reported for planar enhancement-mode CdS transistors. The response time of the photodetector is reduced to the submicrosecond level, 1 order of magnitude shorter than the best results ever reported for photodetectors made of bottom-up semiconductor nanostructures. Guided semiconductor nanowalls open new opportunities for high-performance 3D nanodevices assembled from the bottom up.
| Original language | English |
|---|---|
| Pages (from-to) | 15958-15967 |
| Number of pages | 10 |
| Journal | J. Am. Chem. Soc |
| Volume | 139 |
| Issue number | 44 |
| DOIs | |
| Publication status | Published - 8 Nov 2017 |
Funding
We thank Dr. Iddo Pinkas for the construction of AOM laser and Dr. Yishay Feldman for help with XRD measurements. This research was supported by European Research Council (ERC) Advanced Grant No. 338849, the Israel Science Foundation, Minerva Stiftung, Kimmel Center for Nanoscale Science, Moskowitz Center for Nano and Bio-Nano Imaging, and the Perlman Family Foundation. E.J. is an incumbent of the Drake Family Professorial Chair in Nanotechnology. We thank Editage (www.editage.com) for English language editing.